EDN

Cell-aware ATPG test methods improve test quality

Traditional IC pattern-generation methods focus on detectingdefects at gate terminals or at interconnects. Unfortunately, a significantpopulation of defects may occur within an IC's gates, or cells.
Design-Reuse

Magma Unveils Talus ATPG and Talus ATPG-X – Expands Design-for-Test Capabilities with Physically Aware ATPG and On-Chip Compression

Advanced ATPG products support simultaneous analysis of multiple fault models, leverage multi-threading and on-chip compression to improve quality and reduce turnaround time and costs of nanometer ICs ...
EDN

Design for test boot camp, part 3: Advanced fault models and cell-aware test

The IDDQ test relies on measuring the supply current (I DD) of an IC’s quiescent state, when the circuit isn’t switching and inputs are held at static values. Test patterns are used to place the ...
Design-Reuse

ATPG Challenges at Lower Technology Nodes

With regards to the ongoing trend of diminishing transistor geometries, we are witnessing a sharp increase in defect density along with significant on-chip process variations that affect transistor ...
Semiconductor Engineering

Power-Aware Revolution In Automated Test For ICs

As semiconductor devices advance in complexity and sensitivity to power fluctuations, the integration of power-aware automatic test pattern generation (ATPG) is becoming indispensable for yield and ...
CIOL

Synopsys improves quality of manufacturing tests

MOUNTAIN VIEW, USA: Synopsys Inc. has announced the availability of its TetraMAX small delay defect automatic test pattern generator (ATPG) for use by design organizations worldwide to significantly ...
Semiconductor Engineering

A Simple Way To Improve Automotive In-System Test

Test points for hybrid ATPG/LBIST applications make it easier to reach the ISO 26262 standard of 90% stuck-at coverage for in-system test. The remarkable growth in automotive IC design has prompted a ...