Researchers argue that 'at least 40%' of the bloated x86 ISA could be removed and emulated to improve CPU efficiency

The researchers "conclude that at least 40% of the x86 ISA, even after excluding multimedia extensions, could be emulated ...
CRN

Intel Details Future Interconnect, Instruction Set Plans

At the Intel Developer Forum, Pat Gelsinger, Intel senior vice president and general manager of the Digital Enterprise group, said the Santa Clara, Calif. chipmaker is busy developing new instruction ...
TechSpot

Intel AVX10, APX are the next step in the x86 instruction set evolution

Why it matters: Intel is gearing up for what the company considers the "next major step" in the evolution of the original x86 instruction set architecture (ISA). The Santa Clara corporation is ...
CRN

Analysis: After Big Nvidia Win, Will Intel Ever Escape Its Rival’s Shadow?

While the newly announced Intel-Nvidia deal will help drive CPU sales for Intel, the agreement will nevertheless keep the CPU ...
TechSpot

Intel is reportedly disabling AVX-512 instruction set on Alder Lake CPUs

In brief: Intel 12th Gen Core desktop processors never officially supported AVX-512, but we have workarounds to enable this instruction set. However, new firmware releases might render these methods ...
Semiconductor Engineering

Implementing Cryptographic Algorithms for the RISC-V Instruction Set Architecture in Two Cases

This new technical paper titled “Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms” was published by researchers at Intel, North Arizona University and Google, with ...
Computer Weekly

RISC-V rises to software ecosystem challenge

RISC-V, the open standard instruction set architecture (ISA) alternative to Intel and ARM, held its first European summit on 5 to 9 June 2023 in Barcelona. Originally developed in 2010 at University ...