Synopsys and TSMC have partnered to accelerate the development of next-generation AI chips and multi-die designs.

Cadence (CDNS) announced major advancements in chip design automation and IP, driven by its long-standing relationship with TSMC (TSM) to develop ...

Ansys RedHawk-SC and Ansys Totem power integrity platforms are certified for the latest TSMC N3C, N3P, N2P, and A16 process ...

Learn real-world strategies about FPGA Chip Design, Join Elektor Engineering Insights on Sept 24 at 16:00 CEST with Kevin ...

Launching a pilot 'chip design to tapeout' flow curriculum, enabling academic institutions with industry-aligned coursework. Pilot testing underway at over 40 select worldwide universities with intent ...

Microsoft says it has developed a breakthrough microfluidics cooling system for chips, resembling the veins in a leaf and ...

Learn real-world strategies about FPGA Chip Design, Join Elektor Engineering Insights on Sept 24 at 16:00 CEST with Kevin ...

Researchers say microfluidics could boost efficiency and improve sustainability for next-generation AI chips. Most GPUs operating in today’s datacenters are currently cooled with cold plates, which ...

Though the process of designing a chip using open-source tools may seem daunting at first, it’s an invaluable learning experience and can lead to creation of foundational chips like Silicluster.

"Moving from 7nm and 5nm chips to 2nm means India is stepping into a zone that only a few countries have reached," said a ...

Microsoft says it may have found a better way to keep future AI chips cool, and it involves letting coolant flow right through the chip itself. Instead of attaching a heat sink on top, which adds ...